1. Field of the Invention
This invention relates to a standard cell type semiconductor integrated circuit in which an LSI having desired functions is designed by combining standard cells such as inverter circuits, AND circuits and OR circuits, and particularly to the placement of a plurality of cells and the wiring between the cells.
2. Description of the Related Art
Recently, a poly-cell layout system in which a function block having a desired function is constructed by combining standard cells such as inverter circuits, AND circuits and OR circuits by use of the computer-aided design (CAD) has been developed.
FIG. 9 shows the poly-cell layout. In this layout, a plurality of standard cells (which are hereinafter simply referred to as cells) 12a, 12b, - - -, 12e are placed in an X direction to form a cell row 13a on a substrate 11. A power source line 12.sub.1, ground line 12.sub.2 and signal terminals 12.sub.3 are provided for each of the cells 12a, 12b, - - -, 12e, and the power source lines 12.sub.1 and ground lines 12.sub.2 of the cells are shown to be automatically connected in a continuous form when the cells 12a, 12b, - - -, 12e are placed. Likewise, on the substrate 11, cell rows 13b and 13c are paced in positions apart from the cell row 13a by preset distances in a y direction. The cell row 13b is constructed by cells 12f, 12g, - - -, 12j and the cell row 13c is constructed by cells 12k, 12l, - - -, 12o. Also, a power source line 12.sub.1, ground line 12.sub.2 and signal terminals 12.sub.3 are previously provided for each of the cells 12.sub.f to 12o.
An area between the cell rows 13a and 13b is defined as a first wiring area 14a and an area between the cell rows 13b and 13c is defined as a second wiring area 14b. The respective cells are interconnected by use of the first and second wiring areas 14a and 14b.
FIG. 10 shows interconnections between the cells 12a to 12o and between the cell rows 13a to 13c. That is, first layer metal wirings 15 indicated by broken lines are formed in the first and second wiring areas 14a and 14b. An insulative layer (not shown) is formed on the first metal wiring layers 15, and second layer metal wirings 17 indicated by solid lines are formed on the insulative layer. The first layer metal wirings 15 are selectively connected to the second layer metal wirings 17 through respective through holes 16 formed on the insulative layer. The second layer metal wirings 17 are connected to the signal terminals 12.sub.3 formed on the respective cells 12. Further, the power source lines 12.sub.1 of the cell rows 13a to 13c are connected together in the peripheral area of the substrate 11 and the ground lines 12.sub.2 thereof are also connected together in the peripheral area.
FIG. 11 shows an example of the cell 12 used in the poly-cell layout, and portions which are the same as those of FIGS. 9 and 10 are denoted by the same reference numerals.
In the cell 12, the positions of the power source line 12.sub.1 and the ground line 12.sub.2 are predetermined and the signal terminals 12.sub.3 are arranged on an area excluding the power source line 12.sub.1 and ground line 12.sub.2. In FIG. 11, 91 denotes diffused layers, 92 polysilicon layers, 93 a buried contact, and 94 a position in which impurity ions for forming a depletion type transistor are implanted.
As shown in FIGS. 9 and 10, useless areas may occur in the wiring areas between the cell rows when higher cells and lower cells are placed.
Further, it is necessary to connect the power source lines which are previously provided for the respective cells together and the ground lines which are previously provided for the respective cells together, the rotation of the cells is limited by the power source lines and ground lines. Therefore, when the cells are connected to each other, some wiring lines must take a roundabout way and it is difficult to connect the cells to each other in the shortest way.
In principle, the widths of the power source line and ground line previously provided for each of the cells may be sufficient only if the power source line and ground line can pass a dissipating current of the cell. That is, in a case of the cell row 13a shown in FIGS. 9 and 10, the widths of the power source line and ground line of the cell 12e can be made smaller than those of the cell 12a when a current is supplied from the side of the cell 12a. However, the widths of the power source line and ground line of each cell are so determined that the power source line and ground line can pass a current for the whole portion of one cell row. Therefore, areas occupied by the power source line and ground line are large and it is difficult to reduce the size of the cell itself.